In the conventional boost PFC circuits, the rectifying bridge loss becomes one of the main losses of the switching mode power supply. Following the requirements regarding the convention efficiency are improved, the bridgeless boost topology deriving from the conventional boost PFC circuit has gradually become the focus of the R&D. The bridgeless boost topology omits the rectifying bridge in the front stage of the boost PFC circuit, decreases the loss of a diode, and increases the efficiency. And a dual boost PFC (DBPFC) circuit belongs to a kind of bridgeless boost topologies (please refer to FIG. 1). In FIG. 1, the bridgeless PFC circuit receives the input voltage Vin, generates the output voltage Vo, and includes diodes D1-D4, switches S1-S2, inductors L1-L2 and an output capacitor Co.
In the applications for the medium and small power occasions, the conventional boost PFC topology is widely applied due to its simple configuration, better stability and smaller switch stress. In the CRM, the inductor current has to be decreased to zero before the next period begins. Since the MOSFET can not be turned on before the inductor current reaching zero and there is no reverse recovery loss of the boost rectifying diode, the efficiency in this mode is higher. Besides, since there is no dead time between periods, the current of AC circuit is continuous, and a triangle wave is flowing through the winding. The PFC circuit will adjust the amplitudes of these triangle waves to make the winding current be a sinusoidal wave (after rectifying) in average (please refer to FIG. 2, and the meanings of the regions of the triangle wave, and the names of the waveforms and the traverse axle are shown therein).
In the conventional boost PFC circuit, a method of measuring the voltage of the auxiliary winding of the boost inductor is usually employed to judge the zero-crossing time of the inductor current so as to realize the CRM controlling. The polarity of the auxiliary winding of the inductor is reversed to the polarity of the inductor. The voltage of the auxiliary winding is negative and is proportional to the amplitude of rectified AC voltage when the MOSFET is turned on. The sensed voltage of the auxiliary winding is positive and is proportional to a difference between the output voltage and the rectified AC voltage amplitude when the MOSFET is turned off. The parasitic capacitance at the output terminal of the MOSFET (the parasitic capacitance between drain terminal and source terminal of MOSFET) is resonant with the boost inductor when the inductor current reaches zero. The voltage of the auxiliary winding is decreased due to the resonance. A signal for turning on the MOSFET is sending out when the voltage of the auxiliary winding is lower than a threshold voltage set up by the IC so as to realize the CRM controlling. This kind of method is employed by many ICs, e.g., L6561, FAN7528, NCP1606, UCC38050etc. (please refer to FIG. 3). FIG. 3 is a schematic circuit diagram of a conventional boost PFC circuit realizing the CRM controlling through measuring the voltage of the auxiliary winding of the boost inductor. In FIG. 3, the PFC circuit receives an input voltage Vin and generates an output voltage Vo, and includes diodes D1-D6, resistors R1-R6 and RZCD, switch S1, IC FAN7529 (having terminals VCC, MOT, COMP, GND, CS, INV, and ZCD), inductor L1 and auxiliary winding NAUX and capacitors C1-C2 and Co, wherein GND is the grounding terminal.
FIGS. 4(a)-4(b) are schematic circuit diagrams showing the statuses of the positive half-cycle and the negative half-cycle of a period of frequency of the conventional dual boost PFC circuit respectively. The elements included in FIGS. 4(a)-4(b) are the same as those of FIG. 1, wherein the driving signals of the switches S1 and S2 have the same phase. L1, D3, D1, S1 and C1 form a boost circuit when the input voltage is in its positive half-cycle. The current flows through L1 and S1 when S1 turns on, and there are two returning paths, one is returning via D1 and the other is returning via S2 and L2. The current flows through L1, D3 and C1 when S1 turns off, and the returning paths are the same as above-mentioned, one is returning via D1 and the other is returning via the body diode of S2 and L2. L2, D4, S2, D2 and C1 form another boost circuit when the input voltage is in its negative half-cycle. The current flows through L2 and S2 when S2 turns on, and one of the returning paths is returning via D2 and the other is returning via S1 and L1. The current flows through L2, D4 and C1 when S2 turns off, and one of the returning paths is returning via D2 and the other is returning via the body diode of S1 and L1. Due to that D1 and D2 clamp the AC power source to the negative output terminal of the boost circuit, a common mode noise, which is the same as the conventional boost PFC circuit, could be obtained. Since the current flows through only two elements during a switch period, the conduction loss is decreased.
FIG. 5 is a schematic circuit diagram of a conventional dual boost PFC circuit realizing the CRM controlling via employing a current transformer (CT). Except for a portion which is the same as that of FIG. 1, it further includes an RS flip-flop, a comparator, an error amplifier (EA) and three CTs CT1-CT3. Since the dual boost PFC circuit has three current subcircuits during the positive and negative half-cycles of the input voltage, the three corresponding CTs CT1-CT3 must be used to sample the inductor current so as to turn on the MOSFET for realizing the CRM controlling. The turn-off time period of MOSFET is determined by the ramp signal and the output signal Vcomp of the error amplifier EA.
FIG. 6 is the waveform diagram of the controlling signals of the circuit as shown in FIG. 5, which includes the inductor current (signal), CT signal, the ramp signal, Q1 driving (signal) and Q2 driving (signal). Because the inductor current signal is sampled through the CT, its amplitude is varied according to the high/low of the input AC voltage and the light/heavy of the output load. The inductor current signal is easy to be interfered by the noise when the amplitude of inductor current is quite small such that the turn-on of the MOSFET produces error implementation and the zero-current switching (ZCS) condition is lost. When the input voltage is quite high, the descending slope of the inductor current is decreased slowly. Due to that the measuring threshold value is quite small, MOSFET is turned on before the inductor current decreases to zero, which will increase the turn-on loss.
FIG. 7 is a waveform diagram showing a failure of measuring the inductor current reaching zero under high input voltage and full-load condition (264Vin and 310 W load) of the circuit as shown in FIG. 5.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived a bridgeless power factor correction circuit for a CRM and a controlling method thereof.